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iso 7816 compatible xicor, inc. 1999 patents pending 9900-5004.2 1/26/99 ep 1 characteristics subject to change without notice 1k x76f102 128 x 8 bit functional diagram secure serialflash features 64-bit password security one array (112 bytes) two passwords (16 bytes) read password write password programmable passwords retry counter register allows 8 tries before clearing of the array 32-bit response to reset (rst input) 8 byte sector write mode 1mhz clock rate 2 wire serial interface low power cmos 2.0 to 5.5v operation standby current less than 1? active current less than 3 ma high reliability endurance: 100,000 write cycles data retention: 100 years available in: 8 lead pdip, soic, msop, tssop, and smart card module description the x76f102 is a password access security supervisor, containing one 896-bit secure serialflash array. access to the memory array can be controlled by two 64-bit passwords. these passwords protect read and write operations of the memory array. the x76f102 features a serial interface and software protocol allowing operation on a popular two wire bus. the bus signals are a clock input (scl) and a bidirec- tional data input and output (sda). the x76f102 also features a synchronous response to reset providing an automatic output of a hard-wired 32-bit data stream conforming to the industry standard for memory cards. the x76f102 utilizes xicors proprietary direct write tm cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. logic cs scl sda rst interface 8k byte data transfer array access enable reset response register password array and password verification logic chip enable retry counter serialflash array 32 byte serialflash array array 0 array 1 (password protected) (password protected) 7025 fm 0 1 logic scl sda rst interface 112 byte data transfer array access enable iso reset response register password array and password verification logic retry counter erase logic eeprom array
x76f102 2 pin descriptions serial clock (scl) the scl input is used to cloc k all data into and out of the de vice . serial data (sda) sd a is an open dr ain ser ial data input/output pin. dur ing a read cycle , data is shifted out on this pin. dur ing a wr ite cycle , data is shifted in on this pin. in all other cases , this pin is in a high impedance state . reset (rst) rst is a de vice reset pin. when rst is pulsed high the x76f102 will output 32 bits of x ed data which conf or ms to the standard f or ?ynchronous response to reset? the par t m ust not be in a wr ite cycle f or the response to reset to occur . see figure 7. if there is po w er interr upted dur- ing the response to reset, the response to reset will be abor ted and the par t will retur n to the standb y state . the response to reset is "mask prog r ammab le" only! the basic sequence is illustr ated in figure 1. device operation the x76f102 memor y arr a y consists of f our teen 8-b yte sectors . read or wr ite access to the arr a y alw a ys begins at the rst address of the sector . read oper ations then can contin ue inde nitely . wr ite oper ations m ust total 8 b ytes . there are tw o pr imar y modes of oper ation f or the x76f102; protected read and protected write. pro- tected oper ations m ust be perf or med with one of tw o 8-b yte pass w ords . the basic method of comm unication f or the de vice is gener ating a star t condition, then tr ansmitting a com- mand, f ollo w ed b y the correct pass w ord. all par ts will be shipped from the f actor y with all pass w ords equal to ?? the user m ust perf or m a ck p olling to deter mine the v alidity of the pass w ord, bef ore star ting a data tr ansf er (see ac kno wledge p olling.) only after the correct pass- w ord is accepted and a a ck polling has been perf or med, can the data tr ansf er occur . t o ensure the correct comm unication, rst m ust remain lo w under all conditions e xcept when r unning a ?esponse to reset sequence? data is tr ansf erred in 8-bit segments , with each tr ansf er being f ollo w ed b y an a ck, gener ated b y the receiving de vice . if the x76f102 is in a non v olatile wr ite cycle a ?o a ck (sd a=high) response will be issued in response to load- ing of the command b yte . if a stop is issued pr ior to the non v olatile wr ite cycle the wr ite oper ation will be ter mi- nated and the par t will reset and enter into a standb y mode . pin names pin configuration symbol description sda serial data input/output scl serial clock input rst reset input vcc supply voltage vss ground nc no connect sda v cc rst scl nc 1 2 3 4 7 8 6 5 soic v cc rst scl v ss nc sda smart card module nc nc nc gnd sda v cc rst scl nc 1 2 3 4 7 8 6 5 msop v ss nc nc rst scl sda vss 1 2 3 4 7 8 6 5 pdip v cc nc nc nc nc v ss rst sda nc nc 1 2 3 4 7 8 6 5 v cc scl nc tssop
x76f102 3 after each tr ansaction is completed, the x76f102 will reset and enter into a standb y mode . this will also be the response if an unsuccessful attempt is made to access a protected arr a y . figure 1. x76f102 device operation retry counter the x76f102 contains a retr y counter . the retr y counter allo ws 8 accesses with an in v alid pass w ord bef ore an y action is tak en. the counter will increment with an y com- bination of incorrect pass w ords . if the retr y counter o v er- o ws , the memor y area and both of the pass w ords are cleared to "0". if a correct pass w ord is receiv ed pr ior to retr y counter o v er o w , the retr y counter is reset and access is g r anted. device protocol the x76f102 suppor ts a bidirectional b us or iented pro- tocol. the protocol de nes an y de vice that sends data onto the b us as a tr ansmitter and the receiving de vice as a receiv er . the de vice controlling the tr ansf er is a master and the de vice being controlled is the sla v e . the master will alw a ys initiate data tr ansf ers and pro vide the cloc k f or both tr ansmit and receiv e oper ations . theref ore , the x76f102 will be considered a sla v e in all applications . clock and data conventions data states on the sd a line can change only dur ing scl lo w . sd a changes dur ing scl high are reser v ed f or indicating star t and stop conditions . ref er to figure 2 and figure 3. start condition all commands are preceeded b y the star t condition, which is a high to lo w tr ansition of sd a when scl is high. the x76f102 contin uously monitors the sd a and scl lines f or the star t condition and will not respond to an y command until this condition is met. a star t ma y be issued to ter minate the input of a control b yte or the input data to be wr itten. this will reset the de vice and lea v e it ready to begin a ne w read or wr ite command. because of the push/pull output, a star t can- not be gener ated while the par t is outputting data. star ts are inhibited while a wr ite is in prog ress . stop condition all comm unications m ust be ter minated b y a stop condi- tion. the stop condition is a lo w to high tr ansition of sd a when scl is high. the stop condition is also used to reset the de vice dur ing a command or data input sequence and will lea v e the de vice in the standb y po w er mode . as with star ts , stops are inhibited when outputting data and while a wr ite is in prog ress . acknowledge ac kno wledge is a softw are con v ention used to indicate successful data tr ansf er . the tr ansmitting de vice , either master or sla v e , will release the b us after tr ansmitting eight bits . dur ing the ninth cloc k cycle the receiv er will pull the sd a line lo w to ac kno wledge that it receiv ed the eight bits of data. the x76f102 will respond with an ac kno wledge after recognition of a star t condition and its sla v e address . if both the de vice and a wr ite condition ha v e been selected, the x76f102 will respond with an ac kno wledge after the receipt of each subsequent eight-bit w ord. lo ad command/address byte lo ad 8-byte p assw ord verify p assw ord a ccept ance by use of a ck polling read/write d a t a bytes
x76f102 4 figure 2. data validity figure 3. definition of start and stop conditions table 1. x76f102 instruction set illegal command codes will be disregarded. the par t will respond with a ?o-a ck to the illegal b yte and then retur n to the standb y mode . all wr ite/read oper ations require a pass w ord. command after start command description password used 1 0 0 s 3 s 2 s 1 s 0 0 sector write write 1 0 0 s 3 s 2 s 1 s 0 1 sector read read 1 1 1 1 1 1 0 0 change write password write 1 1 1 1 1 1 1 0 change read password write 0 1 0 1 0 1 0 1 password ack command none scl sd a data stab le data change scl sd a star t condition stop condition program operations sector write the sector wr ite mode requires issuing the 8-bit wr ite command f ollo w ed b y the pass w ord and then the data b ytes tr ansf erred as illustr ated in gure 4. the wr ite com- mand b yte contains the address of the sector to be wr it- ten. data is wr itten star ting at the rst address of a sector and eight b ytes m ust be tr ansf erred. after the last b yte to be tr ansf erred is ac kno wledged a stop condition is issued which star ts the non v olatile wr ite cycle . if more or less than 8 b ytes are tr ansf erred, the data in the sector remains unchanged. ack polling once a stop condition is issued to indicate the end of the host s wr ite sequence , the x76f102 initiates the inter nal non v olatile wr ite cycle . in order to tak e adv antage of the typical 5ms wr ite cycle , a ck polling can begin immedi- ately . this in v olv es issuing the star t condition f ollo w ed b y
x76f102 5 the ne w command code of 8 bits (1st b yte of the proto- col.) if the x76f102 is still b usy with the non v olatile wr ite oper ation, it will issue a ?o-a ck in response . if the non- v olatile wr ite oper ation has completed, an ? ck will be retur ned and the host can then proceed with the rest of the protocol. after the pass w ord sequence , there is alw a ys a non v ola- tile wr ite cycle . this is done to discour age r andom guesses of the pass w ord if the de vice is being tampered with. in order to contin ue the tr ansaction, the x76f102 requires the master to perf or m a pass w ord a ck polling sequence with the speci c command code of 55h. as with regular ac kno wledge polling the user can either time out f or 10ms , and then issue the a ck polling once , or contin uously loop as descr ibed in the o w . if the pass w ord that w as inser ted w as correct, then an ? ck will be retur ned once the non v olatile cycle in response to the pass wrod a ck polling sequence is o v er . if the pass w ord that w as inser ted w as incorrect, then a ?o a ck will be retur ned e v en if the non v olatile cycle is o v er . theref ore , the user cannot be cer tain that the pass- w ord is incorrect until the 10ms wr ite cycle time has elapsed. read operations read oper ations are initiated in the same manner as wr ite oper ations b ut with a diff erent command code . sector read with sector read, a sector address is supplied with the read command. once the pass w ord has been ac kno wl- edged data ma y be read from the sector . an ac kno wl- edge m ust f ollo w each 8-bit data tr ansf er . a read oper ation alw a ys begins at the rst b yte in the sector , b ut ma y stop at an y time . random accesses to the arr a y are not possib le . contin uous reading from the arr a y will retur n data from successiv e sectors . after reading the last sector in the arr a y , the address is automatically set to the rst sector in the arr a y and data can contin ue to be read out. after the last bit has been read, a stop condition is gener ated without sending a preceding ac kno wledge . data a ck p olling sequence a ck retur ned? issue ne w command code wr ite sequence completed enter a ck p olling issue st ar t no yes pr oceed passwor d ack polling sequence a ck retur ned? issue p ass w ord a ck command p ass w ord load completed enter a ck p olling issue st ar t no yes pr oceed
x76f102 6 figure 4. sector write sequence (password required) figure 5. acknowledge polling figure 6. sector read sequence (password required) a ck p st ar t write a ck a ck a ck a ck wr ite p ass w ord 7 wr ite p ass w ord 0 a ck s sd a . . . w ait t wc or a ck p ass w ord command st ar t password ack a ck s command no-a ck if a ck, then p ass w ord matches command st op host commands host commands x76f102 responce x76f102 response a ck a ck a ck w ait t wc data a ck p olling 8th clk. of 8th pwd. b yte ? ck clk 8th clk ? ck clk ? ck st ar t condition 8th bit a ck or no a ck scl sd a data n a ck p st ar t read a ck a ck a ck a ck read p ass w ord 7 read p ass w ord 0 a ck data 0 s sd a . . . w ait t wc or a ck p ass w ord command st ar t password ack a ck s command no-a ck if a ck, then p ass w ord matches command st op host commands host commands x76f102 responce x76f102 response
x76f102 7 passwords p ass w ords are changed b y sending the "change read pass w ord" or "change wr ite pass w ord" commands in a nor mal sector wr ite oper ation. a full eight b ytes contain- ing the ne w pass w ord m ust be sent, f ollo wing successful tr ansmission of the current wr ite pass w ord and a v alid pass w ord a ck response . the user can use a repeated a ck p olling command to chec k that a ne w pass w ord has been wr itten correctly . an a ck indicates that the ne w pass w ord is v alid. there is no wa y to read an y of the pass w or ds. response to reset (default = 19 02 aa 55) the iso response to reset is controlled b y the rst and clk pins . when rst is pulsed high dur ing a cloc k pulse , the de vice will output 32 bits of data, one bit per cloc k, and it resets to the standy state . this conf or ms to the iso standard f or ?ynchronous response to reset? the par t m ust not be in a wr ite cycle f or the response to reset to occur . after initiating a non v olatile wr ite cycle the rst pin m ust not be pulsed until the non v olatile wr ite cycle is complete . if not, the iso response will not be activ ated. if the rst is pulsed high and the clk is within the rst pulse (meet the t nol spec.) in the middle of an iso tr ansaction, it will output the 32 bit sequence again (star ting at bit 0). otherwise , this abor ts the iso oper ation and the par t retur ns to standb y state . if the rst is pulsed high and the clk is outside the rst pulse (in the middle of an iso tr ansaction), this abor ts the iso oper ation and the par t retur ns to standb y state . if there is po w er interr upted dur ing the response to reset, the response to reset will be abor ted and the par t will retur n to the standb y state . a response to reset is not a v ailab le dur ing a non v olatile wr ite cycle . figure 7. response to reset (rst) sck so rst byte 0 msb lsb lsb msb 1 lsb msb lsb msb 2 3 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 1 1 0 absolute maximum ratings* t emper ature under bias ..................... ?5? to +135? stor age t emper ature .......................... ?5? to +150? v oltage on an y pin with respect to v ss ....................................... ?v to +7v d .c . output current .................................................. 5ma lead t emper ature (solder ing, 10 seconds) .................................. 300? *comment stresses abo v e those listed under ?bsolute maxim um ratings ma y cause per manent damage to the de vice . this is a stress r ating only and the functional oper ation of the de vice at these or an y other conditions abo v e those listed in the oper ational sections of this speci cation is not implied. exposure to absolute maxim um r ating condi- tions f or e xtended per iods ma y aff ect de vice reliability .
x76f102 8 recommended operating conditions 7025 fm t06 temp min. max. commercial 0? +70? industrial ?0? +85? supply voltage limits x76f102 4.5v to 5.5v x76f102 ?2 2.0v to 5.5v d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) capacitance t a = +25?, f = 1mhz, v cc = 5v no tes: (1) must perf or m a stop command after a read command pr ior to measurement (2) v il min. and v ih max. are f or ref erence only and are not tested. (3) this par ameter is per iodically sampled and not 100% tested. symbol parameter limits units test conditions min. max. i cc1 v cc supply current (read) 1 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = v ss i cc2 (3) v cc supply current (write) 3 ma f scl = v cc x 0.1/v cc x 0.9 levels @ 400 khz, sda = open rst = v ss i sb1 (1) v cc supply current (standby) 1 ? v il = v cc x 0.1, v ih = v cc x 0.9 f scl = 400 khz, f sda = 400 khz i sb2 (1) v cc supply current (standby) 1 ? v sda = v s cc = v cc other = gnd or v cc ?.3v i li input leakage current 10 ? v in = v ss to v cc i lo output leakage current 10 ? v out = v ss to v cc v il (2) input low voltage ?.5 v cc x 0.1 v v ih (2) input high voltage v cc x 0.9 v cc + 0.5 v v ol output low voltage 0.4 v i ol = 3ma symbol test max. units conditions c out (3) output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (rst, scl) 6 pf v in = 0v equivalent a.c. load circuit a.c. test conditions 3v 1.3k w output 100pf 5v 1.53k w output 100pf input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing level v cc x 0.5 output load 100pf
x76f102 9 ac characteristics (t a = -40?c to +85?c , v cc = +3.0v to +5.5v , unless otherwise speci ed. ) notes: 1. c b = total capacitance of one b us line in pf 2. t aa = 1.1? max belo w v cc = 3.0v . reset ac specifications power up timing notes: 1. dela ys are measured from the time v cc is stab le until the speci ed oper ation can be initiated. these par ameters are per iodically sampled and not 100% tested. 2. t ypical v alues are f or t a = 25?c and v cc = 5.0v nonvolatile write cycle timing notes: 1. t wc is the time from a v alid stop condition at the end of a wr ite sequence to the end of the self-timed inter nal non v olatile wr ite cycle . it is the minim um cycle time to be allo w ed f or an y non v olatile wr ite b y the user , unless ac kno wledge p olling is used. symbol parameter min max units f scl scl clock frequency 0 1 mhz t aa(2) scl low to sda data out valid 0.1 0.9 m s t buf time the bus must be free before a new transmission can start 1.2 m s t hd:sta start condition hold time 0.6 m s t low clock low period 1.2 m s t high clock high period 0.6 m s t su:sta start condition setup time (for a repeated start condition) 0.6 m s t hd:dat data in hold time 10 ns t su:dat data in setup time 100 ns t r sda and scl rise time 20+0.1xc b (1) 300 ns t f sda and scl fall time 20+0.1xc b (1) 300 ns t su:sto stop condition setup time 0.6 m s t dh data out hold time 0 m s t nol rst to scl non-overlap 500 ns t rdv rst low to sda valid during response to reset 0 450 ns t cdv clk low to sda valid during response to reset 0 450 ns t rst rst high time 1.5 m s t su:rst rst setup time 500 ns symbol parameter min. typ (2) max. units t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms symbol parameter min. typ.(1) max. units t wc (1) write cycle time 5 10 ms
x76f102 10 bus timing write cycle timing rst timing diagram ?response to a synchronous reset t su:st a t hd:st a t hd:d a t t su:d a t t lo w t su:st o t r t b uf scl sda in sd a out t dh t aa t f t high scl sd a t wc 8th bit of last b yte a ck stop condition star t condition t rst t nol t high_rst t lo w_rst t cd v t rd v t su:rst d a t a bit (1) d a t a bit (2) 1st clk pulse 2nd clk pulse 3rd clk pulse i/o clk rst t nol
x76f102 11 guidelines for calculating typical values of bus pull up resistors 100 80 60 40 20 bus capacitance in pf pull up resistance in k w r min r max 20 40 60 80 100 r min v ccmax i olmin - - - - - - - - - - - - - - - - - - - - - - - - -1 .8 k w == r max t r c bus - - - - - - - - - - - - - - - - - = t r = maxim um allo w ab le sd a r ise time
x76f102 12 0.118 0.002 (3.00 0.05) 0.040 0.002 (1.02 0.05) 0.150 (3.81) ref . 0.193 (4.90) ref . 0.030 (0.76) 0.036 (0.91) 0.032 (0.81) 0.007 (0.18) 0.005 (0.13) 0.008 (0.20) 0.004 (0.10) 0.0216 (0.55) 7 typ r 0.014 (0.36) 0.118 0.002 (3.00 0.05) 0.012 + 0.006 / -0.002 (0.30 + 0.15 / -0.05) 0.0256 (0.65) typ 8-lead miniature small outline gull wing package type m no te: 1. all dimensions in inches and (millimeters)
x76f102 13 no te: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.020 (0.51) 0.016 (0.41) 0.150 (3.81) 0.125 (3.18) 0.1 10 (2.79) 0.090 (2.29) 0.430 (10.92) 0.360 (9.14) 0.300 (7.62) ref . pin 1 index 0.145 (3.68) 0.128 (3.25) 0.025 (0.64) 0.015 (0.38) pin 1 sea ting plane 0.065 (1.65) 0.045 (1.14) 0.260 (6.60) 0.240 (6.10) 0.060 (1.52) 0.020 (0.51) typ . 0.010 (0.25) 0 15 8-lead plastic du al in-line p a cka ge type p half shoulder width on all end pins optional 0.015 (0.38) max. 0.325 (8.25) 0.300 (7.62)
x76f102 14 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0 ?8 x 45 8-lead plastic small outline gull wing p ackage type s note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050" typical 0.050" typical 0.030" typical 8 places footprint
x76f102 15 note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop , package type v see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .01 18 (.30) 0 ?8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (7.72) all measurements are typical (4.16) (1.78) (0.42)
x76f102 16 0.465 0.002 (11.81 0.05) a section a-a a r. 0.078 (2.00) 0.285 (7.24) max. see no te 7 sht . 2 0.420 0.002 (10.67 0.05) 0.210 0.002 (5.33 0.05) 0.105 0.002 (2.67 0.05) typ . (8x) (8x) 0.105 0.002 (2.67 0.05) 0.008 0.001 (0.20 0.03) 0.233 0.002 (5.92 0.05) 0.174 0.002 (4.42 0.05) 0.146 0.002 (3.71 0.05) die 0.0235 (0.60) max. 0.015 (0.38) max. 0.008 (0.20) max. glob size fr4 tape see det ail sheet 3 copper, nickel pla ted , gold flash r. 0.013 (0.33) (8x) 0.270 (6.86) max. see note 7 sht 2 . 0.069 (1.75) min epoxy free area (typ .) 0.088 (2.24) min epoxy free area (typ.) x76f102 8 p ad chip on bo ard smar t card module type x note: 1. all dimensions in inches and (millimeters) vcc rst scl nc vss nc sd a nc
x76f102 17 note: all measurements in millimeters 8 contact module 11.4 12.6 1.59 0.15 1.215 1.62 1.62 2.54 2.54 90 6 contact module 8 1.3 1.3 0.2 0.2 10.62 1.31 1.31 reject punch position 1.422 1.422 14.25 35 23.02 8.82 4.75 1 35mm tape 35mm tape
x76f102 18 ordering information v cc limits blank = 5v ?0% 2.0 = 2.0v to 5.5v temperature range blank = commercial = 0? to +70? i = industrial= ?0? to +85? package s8 = 8-lead soic m8 = 8-lead msop p = 8-lead pdip v8 - 8-lead tssop h = die in waffle packs w = die in wafer form x = smart card module device x76f102 x x ? part mark convention 8-lead msop acg = 2.0 to 5.5v, 0 to +70? eyww xxx ach = 2.0 to 5.5v, -40 to +85? abs = 4.5 to 5.5v, 0 to +70? abt = 4.5 to 5.5v, -40 to +85? 8-lead soic/pdip x76f102 x xx blank = 8-lead soic f = 2.0 to 5.5v, 0 to +70? g = 2.0 to 5.5v, -40 to +85? blank = 4.5 to 5.5v, 0 to +70? i = 4.5 to 5.5v, -40 to +85? limited w arranty de vices sold b y xicor , inc. are co v ered b y the w arr anty and patent indemni cation pro visions appear ing in its t er ms of sale only . xicor , inc. mak es no w arr anty , e xpress , statutor y , implied, or b y descr iption regarding the inf or mation set f or th herein or regarding the freedom of the descr ibed de vices from patent infr ingement. xicor , inc. mak es no w arr anty of merchantability or tness f or an y pur pose . xicor , inc. reser v es the r ight to discontin ue production and change speci ca- tions and pr ices at an y time and without notice . xicor , inc. assumes no responsibility f or the use of an y circuitr y other than circuitr y embodied in a xicor , inc. product. no other circuits , patents , licenses are implied. u .s. p a tents xicor products are co v ered b y one or more of the f ollo wing u .s . p atents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. f oreign patents and additional patents pending. life rela ted policy in situations where semiconductor component f ailure ma y endanger lif e , system designers using this product should design the system with appropr iate error detection and correction, redundancy and bac k-up f eatures to pre v ent such an occurence .

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